1. Field of the Invention
The disclosures herein generally relate to an image processing apparatus, an image processing method, and a recording medium having an image processing program embodied therein. The disclosures particularly relate to an image processing apparatus, an image processing method, and a recording medium having an image processing program embodied therein by which an interface circuit having a power-saving function is effectively utilized while line isochronism is maintained, thereby improving the power-saving function.
2. Description of the Related Art
In image processing apparatuses such as digital copier machines and digital multifunctional machines, a parallel interface such as a PCI (Peripheral Component Interconnect) has been used as an interface between devices such as a CPU (central processing unit), an image processing module, and a memory.
The parallel interface has problems of racing, skew, etc., so that increases in processing speed and image quality result in the lack of sufficient transfer rate surfacing as a problem for a high-speed, high-image-quality image processing apparatus. In this regard, Japanese Patent Application Publication No. 2005-210653 discloses using for an image processing apparatus a PCI Express (registered trademark: hereinafter referred to as “PCIe”) which is a high-speed serial interface that can issue a next request without waiting for a response because of separation between a request and a response.
PCIe is a standard for connecting between devices through a communication channel referred to as a link, and is defined by PCISIG (Peripheral Component Interconnect Special Interest Group). The PCIe standard sets forth a power management standard such as a transition to a power saving state by use of software and ASPM (active state power management) implemented by use of hardware.
According to the ASPM, the following operations are performed when the ASPM control bit of the configuration resister of a PCIe interface circuit is set to an enable state. Upon passage of a predetermined idle period (i.e., no-data period), the interface circuit and a bus change from the normal state (i.e., active state) to an L0s or L1 state, which is a power saving state. When a need for communication arises in the power saving state, the interface circuit and the bus are moved by hardware from the power saving state to the normal state. Without intervention from software, thus, needless power consumption is reduced during the period in which the interface circuit is idle. This achieves diligent power saving control, thereby improving an effect of reduction of power consumption.
It may be desirable to provide an image processing apparatus, an image processing method, and a recording medium having an image processing program embodied therein by which power saving is achieved for image processing.